FIG. 1 (Background) is a block diagram illustrating an automatic test equipment (“ATE”) 10 coupled with an integrated circuit 12. The fundamental task of an ATE is to test and characterize the functionality of integrated circuits. An ATE is typically a powerful computing platform. Generally speaking, testing an integrated circuit or “chip”, which during a test is referred to as a device under test or “DUT,” involves applying a stimulus, often digital and in the form of a series of logic 1's and 0's, to one or more input pins of the DUT. When the DUT is an analog device, the stimulus applied to the inputs and the expected response are analog and are typically represented by waveforms of varying amplitude or frequency. The DUT generates an output, also typically in the form of a series of logic 1's and 0's, from one or more output pins. The output is captured by the ATE and compared with the expected output to produce test results 14. Characterizing a DUT, in contrast, involves identifying how the DUT reacts to variations in parameters, such as clock speed, voltage levels, and temperature.
Typically, an ATE 10 is physically located at an integrated circuit fabrication facility or “fab.” Purchase of an ATE is a relatively expensive capital equipment expenditure. As such, many fabricators do not dedicate an ATE to testing one particular type of chip, but instead deploy it to test and characterize many different types of chips that each require unique test and characterization routines. Test engineers or other personnel may run tests and characterize some or all of the chips being produced at the fabrication facility.
As new integrated circuits are developed with new features, a fabricator typically attempts to use an existing ATE to test and characterize the new chip. In many instances, the ATE vendor develops new hardware, sometimes referred to as instruments or pin electronics, to interface with the new integrated circuit and allow the ATE to conduct the desired tests. Conventionally, the ATE vendor also has to develop and deploy new software to communicate with the new hardware. It is often time consuming and difficult to adapt existing ATE to the new functionality. One additional problem that often occurs with conventional ATE's involves the difficulty in ensuring that existing test routines for chips being fabricated, perhaps for years, are able to run properly. Oftentimes, the existing routines must be modified and debugged at considerable time and expense to conform with the new software or hardware releases.
Aspects of the present invention provide a software framework or operating system deployable in an ATE that facilitate use of the ATE in testing many different chips, quick and easy reconfiguration of a test or characterization routine to focus on testing of a particular trouble spot for a chip, modularity, test release independence to ease of updating or reconfiguring the ATE to add new features, which might involve adding or upgrading software subroutines and adding or upgrading hardware of the ATE.